1. Field of the Invention
The present invention relates to an image signal processing, and more particularly, to an apparatus and a method for generating a coast signal necessary to controlling the generation of a sampling clock signal used to convert an analog image signal into a digital image signal.
2. Description of the Related Art
An image processing apparatus (not shown) that digitally processes an image signal includes an analog-to-digital converter (ADC) for converting an analog image signal into a digital image signal in response to a sampling clock signal; a phase locked loop (PLL) for generating the sampling clock signal in response to a sync signal; and a scaler for scaling the digital image signal received from the analog-to-digital converter so that the digital image signal can have a pre-defined resolution.
If the sync signal necessary when the phase locked loop generates the sampling clock signal includes a vertical sync signal, the phases of sampling clock signals may be different due to the following reasons.
For the horizontal sync (Hsync) signals and the vertical sync (Vsync)signals to have the same phase, the composite sync (Csync) signal has equalizing pulses around the vertical blanking interval, and serration pulses in the vertical blanking interval. The phases of the horizontal sync signal maybe different around or in the vertical blanking interval because of the vertical sync signal.
Therefore, if the ADC converts the analog image signal into the digital image signal using the sampling clock signal which is generated from an out of phase horizontal sync signal, a part of the display window may be skewed (bent) by the converted digital image signal.
To solve the above problem, it is known to control a phase comparator (detector) in the PLL using a coast signal, masking signal, inhibit signal or a vertical sync signal in order to generate the sampling clock signal from the in phase horizontal sync signal instead of the out of phase horizontal sync signal due to the vertical sync signal. The coast signal refers to the signal which enables the phase locked loop to generate the sampling clock signal using the previous in phase horizontal sync signal, instead of the horizontal sync signal that is out of phase.
An image processor using the coast signal in the PLL as described above is disadvantageous in that it necessitates an additional scaler that generates the coast signal from the composite sync signal. In addition, even though the scaler generates the coast signal in a stable manner, there is the possibility that an out of phase sampling clock signal may be generated.
In case of an image processor which uses the vertical sync signal instead of the coast signal, the out of phase sampling clock signal may be generated if the phase of the vertical sync signal is delayed, or there is an equalizing pulse or a serration pulse or a copy protection pulse in the vertical sync interval.
Incorporated by reference herein are the following references which describe control of a PLL to prevent erroneous phase comparison results due to the vertical sync signal: U.S. Pat. No. 4,253,116 to Robert L. Rogers, III, entitled Televison Synchronizing System Operable From Nonstandard Signals; U.S. Pat. No. 4,809,068 to Hiroshi Nagai entitled Clock Signal Generating Circuit For Television Receiver; U.S. Pat. No. 5,019,907 to Satoshi Murakoshi et al. entitled Pulse Generating Circuit; U.S. Pat. No. 5,663,688 to Christian Delmas, et al. entitled Method Of Enhancing The Noise Immunity OF A Phase-Locked Loop, And Device Implementing This Method; and U.S. Pat. No. 6,222,590 to Yuji Makino entitled Phase-Locked Loop Circuit.